Portable electronic devices, such as notebook computers, personal digital assistants (“PDA”), mobile phones, personal entertainment devices and the like, are becoming more and more popular in recent years. Given its portable nature, a portable electronic device is typically powered by battery when in operation. Battery life is thus a critical factor affecting the usefulness of battery-powered electronic devices. Battery life, in turn, is affected by the rate power is consumed by the various components of the electronic device. Because DRAM is widely used in many portable electronic devices, reducing the power consumed by a DRAM device will generally help reducing the overall power consumption.
In general, the power consumption of a DRAM device increases with both the capacity and the operating speed of the DRAM device. The power consumed by a DRAM device is also affected by its operating mode. A DRAM device, for example, will generally consume a relatively large amount of power when the memory cells of the DRAM device are being refreshed in a refresh mode.
As is well-known in the art, DRAM memory cells, each of which typically comprising a transistor and a capacitor, must be periodically refreshed to retain data stored in the DRAM device. A refresh operation essentially requires reading data bits from the memory cells in each row of a memory cell array and then writing those same data bits back to the same cells in the row. A relatively large amount of power is consumed for a DRAM refresh operation because rows of memory cells in a memory cell array of the DRAM are being actuated in rapid sequence. Each time a row of memory cells is actuated a pair of digit lines for each memory cell are switched to complementary voltages and then equilibrated. As a result, refresh operations of a DRAM device tend to be particularly power-hungry operations. Moreover, because memory cell refreshing must be accomplished even when the DRAM device is not being used (e.g., when the DRAM device is inactive), the amount of power consumed by refresh operation is a critical determinant of the amount of power consumed by the DRAM device over an extended period of time. Thus, many attempts to reduce power consumption in DRAM devices have focused on reducing the rate at which power is consumed during refresh.
The power consumed by a refresh operation can, of course, be reduced by lowering the rate at which the memory cells in a DRAM are being refreshed. However, lowering the refresh rate increases the risk that data stored in the DRAM memory cells will be lost. More specifically, because DRAM memory cells are essentially charge-storing capacitors, electric charge inherently leaks from a memory cell capacitor, which can change the value of a data bit stored in the memory cell over time. Moreover, electrical current typically leaks from the memory cell capacitors at varying rates. Some capacitors are essentially short-circuited and are thus incapable of storing charge indicative of a data bit. These defective memory cells can be detected during production testing, and can be repaired by substituting non-defective memory cells using conventional redundancy circuitry. On the other hand, in general current leaks from most DRAM memory cells at much slower rates that span a wide range. Accordingly, a refresh rate is chosen to ensure that all but a few memory cells can store data bits without the data bits being in error.
One technique that has been adopted to prevent error in the stored data bits is to generate an error correcting code, which is known as a parity code or “syndrome,” from each set of the stored data bits, and then store the syndrome along with the data. When the data bits are read from the memory cells, the corresponding syndrome is also read and used to determine if any bits of the data are in error. As long as not too many data bits are in error, the syndrome may also be used to correct the read data.
In another technique, a sleep mode using error correction circuitry is employed for low-power data retention. The use of error correction circuitry allows the extension of internal refresh period beyond typical refresh characteristics and thereby achieves reduction of power consumption.
When product codes, such as Hamming product codes, are employed as the error correction algorithm, under certain circumstances some errors in data bits cannot be corrected. For example, when four memory cells having erroneous data bits happen to be the cross points of two rows and two columns of memory cells (referred to as “cubic failing bits” hereinafter), error correction is not impossible but usually requires a much more complex error correction circuitry. Although such cubic failing bits can be corrected by erasure error correction using soft decision decoding, a large circuit is required due to the complex calculation involved. Such approach is thus not suitable for implementation in electronic devices using DRAM.
Accordingly, there is a need and desire for a simple correction algorithm as a viable method for erasure error correction that can be implemented in DRAM devices to achieve relatively low power consumption.